3 research outputs found
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Design flow parameters are of utmost importance to chip design quality and
require a painfully long time to evaluate their effects. In reality, flow
parameter tuning is usually performed manually based on designers' experience
in an ad hoc manner. In this work, we introduce a machine learning-based
automatic parameter tuning methodology that aims to find the best design
quality with a limited number of trials. Instead of merely plugging in machine
learning engines, we develop clustering and approximate sampling techniques for
improving tuning efficiency. The feature extraction in this method can reuse
knowledge from prior designs. Furthermore, we leverage a state-of-the-art
XGBoost model and propose a novel dynamic tree technique to overcome
overfitting. Experimental results on benchmark circuits show that our approach
achieves 25% improvement in design quality or 37% reduction in sampling cost
compared to random forest method, which is the kernel of a highly cited
previous work. Our approach is further validated on two industrial designs. By
sampling less than 0.02% of possible parameter sets, it reduces area by 1.83%
and 1.43% compared to the best solutions hand-tuned by experienced designers
WHYPE: A Scale-Out Architecture with Wireless Over-the-Air Majority for Scalable In-memory Hyperdimensional Computing
Hyperdimensional computing (HDC) is an emerging computing paradigm that
represents, manipulates, and communicates data using long random vectors known
as hypervectors. Among different hardware platforms capable of executing HDC
algorithms, in-memory computing (IMC) has shown promise as it is very efficient
in performing matrix-vector multiplications, which are common in the HDC
algebra. Although HDC architectures based on IMC already exist, how to scale
them remains a key challenge due to collective communication patterns that
these architectures required and that traditional chip-scale networks were not
designed for. To cope with this difficulty, we propose a scale-out HDC
architecture called WHYPE, which uses wireless in-package communication
technology to interconnect a large number of physically distributed IMC cores
that either encode hypervectors or perform multiple similarity searches in
parallel. In this context, the key enabler of WHYPE is the opportunistic use of
the wireless network as a medium for over-the-air computation. WHYPE implements
an optimized source coding that allows receivers to calculate the bit-wise
majority of multiple hypervectors (a useful operation in HDC) being transmitted
concurrently over the wireless channel. By doing so, we achieve a joint
broadcast distribution and computation with a performance and efficiency
unattainable with wired interconnects, which in turn enables massive
parallelization of the architecture. Through evaluations at the on-chip network
and complete architecture levels, we demonstrate that WHYPE can bundle and
distribute hypervectors faster and more efficiently than a hypothetical wired
implementation, and that it scales well to tens of receivers. We show that the
average error rate of the majority computation is low, such that it has
negligible impact on the accuracy of HDC classification tasks.Comment: Accepted at IEEE Journal on Emerging and Selected Topics in Circuits
and Systems (JETCAS). arXiv admin note: text overlap with arXiv:2205.1088