Digital On-Chip Calibration of Analog Systems towards Enhanced Reliability

This chapter deals with digital method of calibration for analog integrated circuits as a means of extending its lifetime and reliability, which consequently affects the reliability the analog electronic system as a whole. The proposed method can compensate for drift in circuit’s electrical parameters, which occurs either in a long term due to aging and electrical stress or it is rather more acute, being caused by process, voltage and temperature variations. The chapter reveals the implementation of ultra-low voltage on-chip system of digitally calibrated variable-gain amplifier (VGA), fabricated in CMOS 130 nm technology. It operates reliably under supply voltage of 600mV with 10% variation, in temperature range from −20°C to 85°C. Simulations suggest that the system will preserve its parameters for at least 10 years of operation. Experimental verification over 10 packaged integrated circuit (IC) samples shows the input offset voltage of VGA is suppressed in range of 13μV to 167μV. With calibration the VGA closely meets its nominally designed essential specifications as voltage gain or bandwidth. Digital calibration is comprehensively compared to its widely used alternative, Chopper stabilization through its implementation for the same VGA

Implementation of Autocorrelation-based Feature Detector for Cognitive Radio

Nykyiset ja tulevat langattomat järjestelmät tarvitsevat yhä enemmän taajuuskaistoja uusille palveluille. Lähes koko käytettävissä oleva radiospektri on lisensoitu, mutta suurinta osaa lisensoiduista taajuuskaistoista ei hyödynnetä tehokkaasti tiukkojen käyttöehtojen vuoksi. Kognitiiviset radiot voivat helpottaa tätä ongelmaa, tunnistamalla vajaasti käytetyn kaistan ja ottamalla sen käyttöön häiritsemättä kaistan lisensoinutta käyttäjää. Kognitiivisten radioiden tärkein ominaisuus on löytää vapaat spektrin alueet sekä tunnistaa lisensoitujen käyttäjien lähetykset. Tässä diplomityössä esitetään autokorrelaatioon perustuvan spektrinhavainnointialgoritmin suunnittelu ja toteutus. Algoritmi tunnistaa OFDM-signaaleihin perustuvia järjestelmiä. Toteutuksessa algoritmia on muokattu, ja laskentaa yksinkertaistettu tarvittavan pinta-alan ja tehonkulutuksen pienentämiseksi. Implementaatio ja VHDL kuvaukset verifioidaan simulaatioilla. Algoritmi on toteutettu FPGA kehitysalustalle, ja sen toiminta on varmennettu mittauksilla. Algoritmi toteutettiin myös ASIC-piirinä tehonkulutus- ja pinta-alatietojen saamiseksi. FPGA-toteutus tarvitsee 987 LUT flip-flop paria, ja sen tehonkulutus oli 3.69 mW. ASIC:na piiri toteutettiin 65 nm CMOS prosessilla pinta-alan ollessa 0.26 mm2 ja tehonkulutuksen 1.02 mW.Emerging wireless systems demandmore frequency bands in order to provide high data rate services. Most of the licensed frequency bands are underutilized, because of the rigid spectrum allocation. Cognitive radios aim to relieve the situation by identifying and exploiting the underutilized radio spectrum. A key task of the cognitive radio is spectrum sensing, which is intended to detect unoccupied frequency slots and licensed spectrum user transmissions. This thesis presents an implementation of an autocorrelation-based feature detector for orthogonal frequency-division multiplexing (OFDM) based primary user signals. The autocorrelation-based detection algorithm is optimized in order to achieve power and area efficient hardware realization. The VHDL implementation is presented in detail and verified by simulations. After verification, the algorithm is implemented in a field-programmable gate array (FPGA) evaluation environment, and the performance is verified with measurements. An application-specific integrated circuit (ASIC) implementation is also realized in order to obtain comparable data of power consumption and area. The algorithm implementation with DC offset compensation performed as predicted by simulations. The FPGA implementation requires 987 LUT flip-flop units, and the dynamic power consumption is 3.69 mW. The ASIC circuit implemented with 65 nm CMOS process occupies an area of 0.26 mm2, and has power consumption of 1.02 mW