Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

Digital Predistortion of Millimeter-Wave Phased Antenna Arrays

The cost of deployment of reliable, high-throughput, fifth-generation (5G) millimeter-wave (mm-wave) base stations will depend significantly on the maximum equivalent isotropically radiated power (EIRP) that the base stations can transmit. High EIRP can be generated using active beamforming antenna arrays with large apertures and driven by an array of power amplifiers (PAs). However, given the tight half-wavelength lattice that the arrays must retain to ensure a wide beam steering range, the achievable EIRP quickly becomes thermally-limited. Efficient power amplification is thus imperative to low-cost and reliable beamforming antenna array design. This work considers the application of Digital Predistortion (DPD) as an efficiency-enhancement technique for mm-wave beamforming antenna arrays. Two RF beamforming configurations were considered and corresponding DPD schemes were investigated. First, a single-input single-output (SISO) DPD is proposed that can linearize a single-user RF beamforming array in the presence of non-idealities such as PA load modulation and variation of phase shifter gain with phase. The SISO DPD relies on a feedback signal which reflects a coherent summation of the PA outputs. The SISO DPD is then validated by measurement of a 4-element and 64-element array at 28 GHz with 800 MHz modulated signals using a single over-the-air feedback signal. The SISO DPD uses different sets of coefficients to cope with changes in both linear and non-linear distortions as the beam is steered. Second, the SISO DPD formulation is extended to multi-user RF beamforming to linearize multiple sub-arrays. In this configuration, non-negligible inter-user interference can affect the DPD training. To address the interference, a linear estimate of the interference is calculated and canceled for each user before extracting the SISO DPD coefficients in each sub-array. The SISO DPD with interference cancellation is validated by measurement of a 2-user 2x64-element subarray hybrid at 28 GHz with 800 MHz modulated signals across different combinations of steering angles for the two users