409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS

We present a fast 64b adder based on Output Prediction Logic (OPL) that has a measured worstcase delay of 409ps, equivalent to 4.7 FO4 inverter delays for the TSMC 0.18um process that was used for fabrication. This normalized delay is 1.45X faster than the fastest previously reported 64b adder. The adder uses a modified radix-3 Kogge-Stone architecture and has 5 logic levels. 1