Design and Analysis of Charge Pump and Loop Filter for Wideband PLL

The growing market for wireless applications demands low-cost low-power system-on-chip (SOC) transceiver systems. The frequency synthesizer, used as local oscillator, is one of the most critical building blocks in any integrated transceiver sys-tem. As the demand of low-power low-voltage cost-effective high frequency system increases, design is getting more and more challenging. Due to the high level of integration, digital CMOS process is most favorable for SOC design but it increases the design challenges for RF circuits. This research work is carried out on the design and implementation of low-power low-noise low-cost frequency synthesizer in 0.18μmepi-digital CMOS process. A new scheme has been used to linearize the VCO output frequency versus tuning voltage characteristic, which reduces the VCO gain. Jitter modeling in cadence has been discussed