1 research outputs found
Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity
In modern systems, DRAM-based main memory is significantly slower than the
processor. Consequently, processors spend a long time waiting to access data
from main memory, making the long main memory access latency one of the most
critical bottlenecks to achieving high system performance. Unfortunately, the
latency of DRAM has remained almost constant in the past decade. This is mainly
because DRAM has been optimized for cost-per-bit, rather than access latency.
As a result, DRAM latency is not reducing with technology scaling, and
continues to be an important performance bottleneck in modern and future
systems.
This dissertation seeks to achieve low latency DRAM-based memory systems at
low cost in three major directions. First, based on the observation that long
bitlines in DRAM are one of the dominant sources of DRAM latency, we propose a
new DRAM architecture, Tiered-Latency DRAM (TL-DRAM), which divides the long
bitline into two shorter segments using an isolation transistor, allowing one
segment to be accessed with reduced latency. Second, we propose a fine-grained
DRAM latency reduction mechanism, Adaptive-Latency DRAM, which optimizes DRAM
latency for the common operating conditions for individual DRAM module. Third,
we propose a new technique, Architectural-Variation-Aware DRAM (AVA-DRAM),
which reduces DRAM latency at low cost, by profiling and identifying only the
inherently slower regions in DRAM to dynamically determine the lowest latency
DRAM can operate at without causing failures.
This dissertation provides a detailed analysis of DRAM latency by using both
circuit-level simulation with a detailed DRAM model and FPGA-based profiling of
real DRAM modules. Our latency analysis shows that our low latency DRAM
mechanisms enable significant latency reductions, leading to large improvement
in both system performance and energy efficiency.Comment: 159 pages, PhD thesis, CMU 201