AICPA Committee Handbook Showing All Member History for All Years In Which Electronic Records Have Been Maintained

https://egrove.olemiss.edu/aicpa_comm/1216/thumbnail.jp

Portable High Throughput Digital Microfluidics and On-Chip Bacteria Cultures

An intelligent, portable, and high throughput digital microfluidic (DMF) system is developed. Chapter 1 introduces microfluidics and DMF systems. In Chapter 2, a low-cost and high resolution capacitive-to-digital converter integrated circuit is used for droplet position detection. A field-programmable gate array FPGA is used as the integrated logic hub of the system for highly reliable and efficient control of the circuit. In this chapter a fast-fabricating PCB (printed circuit board) substrate microfluidic system is proposed. Smaller actuation threshold voltages than those previously reported are obtained. Droplets (3 µL) are actuated using 200 V, 500 Hz DC pulses. Droplet positions can be detected and displayed on a PC-based 3D animation in real time. The actuators and the capacitance sensing circuits are implemented on one PCB to reduce the size of the system. In Chapter 3, an intelligent EWOD (electrowetting on dielectric) top plate control system is proposed. The dynamic top plate is controlled by a piezoelectric (PZT) cantilever structure. A high resolution laser displacement sensor is used to monitor the deflection of the top plate. The gap height optimization and the harmonic vibration significantly improve the droplet velocity and decrease the droplet minimum threshold actuation voltage. The top plate vibration induced actuation improvement is magnitude and frequency dependent. 100 µm and 200 µm vibrations are tested at 25 Hz. Vibration frequencies at 5 Hz, 10 Hz, and 20 Hz are tested while the magnitude is 200 µm. Results show greater improvements are achieved at larger vibration magnitudes and higher vibration frequencies. With a vibrated top plate, the largest reduction of the actuation voltage is 76 VRMS for a 2.0 µl DI water droplet. The maximum droplet instantaneous velocity is around 9.3 mm/s, which is almost 3 times faster than the droplet velocity without top plate vibration. Liquid that has different hysteresis such as acetonitrile with various concentrations are used as a control to show its compatibility with the proposed DMF chip. Contact line depinning under top plate vibration is observed, which indicates the underlying mechanism for the improvements in actuation velocity and threshold voltage. The top plate control technique reported in this study makes EWOD DMF chips more reliable for point of care diagnostics. In Chapter 4, the mechanisms of the improvements were investigated by observing the detailed changes in the contact angle hysteresis using both parallel and nonparallel top plates. In Chapter 5, on-chip cell cultures are used for anti-biotic resistant bacteria detection. The passively dispensed on-chip cell cultures realize the isolated micro environment electrochemistry measurement, shorten the culturing time, and reduce the required sample volume. The design of the next generation ultra-portable DMF system is covered in the Appendix. Detailed technical notes and hardware design is covered in the Appendix. The proposed portable and high throughput DMF system with on-chip cell cultures have a great potential to change the standards for micro-environment culturing technologies, which will significantly improve the efficiency of actuation, sensing, and detecting performance of the DMF systems

Lady Griz Volleyball Media Guide, 2004

Media guide created about the Lady Griz volleyball team.https://scholarworks.umt.edu/ladygrizvolleyball_mediaguides/1023/thumbnail.jp

Interdisciplinary Film & Digital Media 2015 APR Self-Study & Documents

UNM Interdisciplinary Film & Digital Media APR self-study report, review team report, response to review report, and initial action plan for Spring 2015, fulfilling requirements of the Higher Learning Commission. IFDM was absorbed by the Cinematic Arts Department following this review

Survey on Instruction Selection: An Extensive and Modern Literature Review

Instruction selection is one of three optimisation problems involved in the code generator backend of a compiler. The instruction selector is responsible of transforming an input program from its target-independent representation into a target-specific form by making best use of the available machine instructions. Hence instruction selection is a crucial part of efficient code generation. Despite on-going research since the late 1960s, the last, comprehensive survey on the field was written more than 30 years ago. As new approaches and techniques have appeared since its publication, this brings forth a need for a new, up-to-date review of the current body of literature. This report addresses that need by performing an extensive review and categorisation of existing research. The report therefore supersedes and extends the previous surveys, and also attempts to identify where future research should be directed.Comment: Major changes: - Merged simulation chapter with macro expansion chapter - Addressed misunderstandings of several approaches - Completely rewrote many parts of the chapters; strengthened the discussion of many approaches - Revised the drawing of all trees and graphs to put the root at the top instead of at the bottom - Added appendix for listing the approaches in a table See doc for more inf

Timing-Driven Macro Placement

Placement is an important step in the process of finding physical layouts for electronic computer chips. The basic task during placement is to arrange the building blocks of the chip, the circuits, disjointly within a given chip area. Furthermore, such positions should result in short circuit interconnections which can be routed easily and which ensure all signals arrive in time. This dissertation mostly focuses on macros, the largest circuits on a chip. In order to optimize timing characteristics during macro placement, we propose a new optimistic timing model based on geometric distance constraints. This model can be computed and evaluated efficiently in order to predict timing traits accurately in practice. Packing rectangles disjointly remains strongly NP-hard under slack maximization in our timing model. Despite of this we develop an exact, linear time algorithm for special cases. The proposed timing model is incorporated into BonnMacro, the macro placement component of the BonnTools physical design optimization suite developed at the Research Institute for Discrete Mathematics. Using efficient formulations as mixed-integer programs we can legalize macros locally while optimizing timing. This results in the first timing-aware macro placement tool. In addition, we provide multiple enhancements for the partitioning-based standard circuit placement algorithm BonnPlace. We find a model of partitioning as minimum-cost flow problem that is provably as small as possible using which we can avoid running time intensive instances. Moreover we propose the new global placement flow Self-Stabilizing BonnPlace. This approach combines BonnPlace with a force-directed placement framework. It provides the flexibility to optimize the two involved objectives, routability and timing, directly during placement. The performance of our placement tools is confirmed on a large variety of academic benchmarks as well as real-world designs provided by our industrial partner IBM. We reduce running time of partitioning significantly and demonstrate that Self-Stabilizing BonnPlace finds easily routable placements for challenging designs – even when simultaneously optimizing timing objectives. BonnMacro and Self-Stabilizing BonnPlace can be combined to the first timing-driven mixed-size placement flow. This combination often finds placements with competitive timing traits and even outperforms solutions that have been determined manually by experienced designers

DETERMINING THE INFLUENCE OF THE NETWORK TIME PROTOCOL (NTP) ON THE DOMAIN NAME SERVICE SECURITY EXTENSION (DNSSEC) PROTOCOL

Recent hacking events against Sony Entertainment, Target, Home Depot, and bank Automated Teller Machines (ATMs) fosters a growing perception that the Internet is an insecure environment. While Internet Privacy Concerns (IPCs) continue to grow out of a general concern for personal privacy, the availability of inexpensive Internet-capable mobile devices increases the Internet of Things (IoT), a network of everyday items embedded with the ability to connect and exchange data. Domain Name Services (DNS) has been integral part of the Internet for name resolution since the beginning. Domain Name Services has several documented vulnerabilities; for example, cache poisoning. The solution adopted by the Internet Engineering Task Force (IETF) to strengthen DNS is DNS Security Extensions (DNSSEC). DNS Security Extensions uses support for cryptographically signed name resolution responses. The cryptography used by DNSSEC is the Public Key Infrastructure (PKI). Some researchers have suggested that the time stamp used in the public certificate of the name resolution response influences DNSSEC vulnerability to a Man-in-the-Middle (MiTM) attack. This quantitative study determined the efficacy of using the default relative Unix epoch time stamp versus an absolute time stamp provided by the Network Time Protocol (NTP). Both a two-proportion test and Fisher’s exact test were used on a large sample size to show that there is a statistically significant better performance in security behavior when using NTP absolute time instead of the traditional relative Unix epoch time with DNSSEC