Review of high-speed phase accumulator for direct digital frequency synthesizer

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed

A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance

This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicongermanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation.Council for Scientific and Industrial Research.http://www.elsevier.com/locate/mejo2016-04-30hb201

A Fully Integrated CMOS Receiver.

The rapidly growing wireless communication market is creating an increasing demand for low-cost highly-integrated radio frequency (RF) communication systems. This dissertation focuses on techniques to enable fully-integrated, wireless receivers incorporating all passive components, including the antenna, and also incorporating baseband synchronization on-chip. Not only is the receiver small in size and requires very low power, but it also delivers synchronized demodulated data. This research targets applications such as implantable neuroprosthetic devices and environmental wireless sensors, which need short range, low data-rate wireless communications but a long lifetime. To achieve these goals, the super-regenerative architecture is used, since power consumption with this architecture is low due to the simplified receiver architecture. This dissertation presents a 5GHz single chip receiver incorporating a compact on-chip 5 GHz slot antenna (50 times smaller than traditional dipole antennas) and a digital received data synchronization. A compact capacitively-loaded 5 GHz standing-wave resonator is used to improve the energy efficiency. An all-digital PLL timing scheme synchronizes the received data clock. A new type of low-power envelope detector is incorporated to increase the data rate and efficiency. The receiver achieves a data rate up to 1.2 Mb/s, dissipates 6.6 mW from a 1.5 V supply. The novel on-chip capacitively-loaded, transmission-line-standing-wave resonator is employed instead of a conventional low-Q on-chip inductor. The simulated quality factor of the resonator is very high (35), and is verified by phase-noise measurements of a prototype 5GHz Voltage Control Oscillator (VCO) incorporating this resonator. The prototype VCO, implemented in 0.13 µm CMOS, dissipates 3 mW from a 1.2 V supply, and achieves a measured phase noise of -117 dBc/Hz at a 1 MHz offset. In the on-chip antenna an efficient shielding technique is used to shield the antenna from the low-resistivity substrate underneath. Two standalone on-chip slot antenna prototypes were designed and fabricated in 0.13 µm CMOS. The 9 GHz prototype occupies a die area of only 0.3 mm2, has an active gain of -4.4 dBi and an efficiency of 9%. The second prototype occupies a die area of 0.47 mm2, and achieves a passive gain of approximately -17.0 dBi at 5 GHz.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60739/1/shid_1.pd

Design of Low-Power Short-Distance Transceiver for Wireless Sensor Networks

Ph.DDOCTOR OF PHILOSOPH

Entwurf eines Empfängers für die drahtlose Datenübertragung bei 60 GHz

Die vorliegende Arbeit befasst sich mit dem Entwurf eines monolithisch integrierten 60-GHz-Empfängerschaltkreises in einer modernen Silizium-Germanium-Halbleitertechnologie mit 190 GHz maximaler Transitfrequenz. Drei für die Entwicklung von MMIC-Empfängerschaltkreisen äußerst wichtige Prinzipien liegen dem Entwurf zugrunde: die Optimierung von Rauschverhalten und Bandbreite sowie die Betrachtung der maximal erreichbaren Ausgangsleistung. Diese Prinzipien werden detailliert untersucht und typische Schaltungen dahingehend analysiert. Insbesondere wird eine Methode vorgestellt, die es erlaubt, die maximale Ausgangsleistung für die häufig verwendete Kaskodestufe vorherzusagen. Dabei handelt es sich um eine Erweiterung der Methode der Lastkurve nach Cripps. Weiterhin werden Ansätze zur Modellierung von Leitungen vorgestellt und ihre Verwendbarkeit für die unterschiedlichen Simulationsarten diskutiert. Der Hauptteil der Arbeit behandelt den Entwurf des Empfängerschaltkreises, welcher aus einem breitbandigen Eingangsverstärker mit niedrigem Rauschen und einstellbarer Verstärkung, einem Leistungsteiler, einem direkten Quadratur-Abwärtsmischer, einem Basisbandverstärker, einem Treiberverstärker für das Lokaloszillatorsignal sowie einem 90°-Phasenschieber besteht. Zusätzlich sind verschiedene Referenzstrom- und -spannungsquellen im Schaltkreis integriert. Die gefertigte Schaltung wurde messtechnisch vollständig charakterisiert, und alle Ergebnisse sind wiedergegeben. Der gemessene Mischgewinn beträgt bis zu 40 dB bei einer Bandbreite von mehr als 15 GHz. Die Zweiseitenbandrauschzahl liegt bei moderaten 7,5 dB. Die gemessene Phasen- und Amplitudenabweichung sind geringer als 5° und geringer als 0,15 dB. Die Gesamtschaltung nimmt 360 mW Leistung aus einer 2,2-V-Spannungsquelle auf. Insbesondere die Bandbreite des Empfängerschaltkreises stellt eine Verbesserung des aktuellen Standes der Technik dar.The present work studies the development of a monolithic 60 GHz receiver IC in a modern 190 GHz-fT silicon-germanium semiconductor technology. The design is based on three fundamental principles, which are of great importance for MMIC receiver design: noise optimisation, bandwidth enhancement and output power considerations. Those principles are discussed in detail, and typical circuit examples are comprehensively analysed. Specifically, a method is presented that allows the prediction of output power for the frequently-used cascode stage. This method is an extension of Cripps’ load line theory. Furthermore, modelling approaches for transmission lines and their suitability for various types of simulations are discussed. The main part focuses on the design process of the receiver IC, which consists of a broadband low noise amplifier with variable gain, a power divider, a zero-IF quadrature mixer, a baseband amplifier, an LO driver amplifier and a 90°-phase shifter. Additionally, several reference current and voltage sources are implemented in the IC. The manufactured circuit is characterised in detail, and all measurement results are presented. Over a bandwidth of more than 15 GHz, the measured conversion gain is up to 40 dB with a moderate double sideband noise figure of 7.5 dB. An I/Q imbalance measurement reveals a phase accuracy of better than 5° and an amplitude error of less than 0.15 dB. The total power consumption is 360 mW from a 2.2 V-source. Particularly in terms of bandwidth, the circuit performance exceeds the current state of the art