1 research outputs found
Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI
The performance and reliability of Ultra-Low-Power (ULP) computing platforms
are adversely affected by environmental temperature and process variations.
Mitigating the effect of these phenomena becomes crucial when these devices
operate near-threshold, due to the magnification of process variations and to
the strong temperature inversion effect that affects advanced technology nodes
in low-voltage corners, which causes huge overhead due to margining for timing
closure. Supporting an extended range of reverse and forward body-bias, UTBB
FD-SOI technology provides a powerful knob to compensate for such variations.
In this work we propose a methodology to maximize energy efficiency at run-time
exploiting body biasing on a ULP platform operating near-threshold. The
proposed method relies on on-line performance measurements by means of Process
Monitoring Blocks (PMBs) coupled with an on-chip low-power body bias generator.
We correlate the measurement performed by the PMBs to the maximum achievable
frequency of the system, deriving a predictive model able to estimate it with
an error of 9.7% at 0.7V. To minimize the effect of process variations we
propose a calibration procedure that allows to use a PMB model affected by only
the temperature-induced error, which reduces the frequency estimation error by
2.4x (from 9.7% to 4%). We finally propose a controller architecture relying on
the derived models to automatically regulate at run-time the body bias voltage.
We demonstrate that adjusting the body bias voltage against environmental
temperature variations leads up to 2X reduction in the leakage power and a 15%
improvement on the global energy consumption when the system operates at 0.7V
and 170MH