12,614 research outputs found
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
Large-capacity Content Addressable Memory (CAM) is a key element in a wide
variety of applications. The inevitable complexities of scaling MOS transistors
introduce a major challenge in the realization of such systems. Convergence of
disparate technologies, which are compatible with CMOS processing, may allow
extension of Moore's Law for a few more years. This paper provides a new
approach towards the design and modeling of Memristor (Memory resistor) based
Content Addressable Memory (MCAM) using a combination of memristor MOS devices
to form the core of a memory/compare logic cell that forms the building block
of the CAM architecture. The non-volatile characteristic and the nanoscale
geometry together with compatibility of the memristor with CMOS processing
technology increases the packing density, provides for new approaches towards
power management through disabling CAM blocks without loss of stored data,
reduces power dissipation, and has scope for speed improvement as the
technology matures.Comment: 10 pages, 11 figure
Self assembled three-dimensional nonvolatile memories
A promising strategy for for the realisation of three-dimensional memories could be the self assembly of articial sub-micron elements (smarticles). Such elements can be realised by combining edge-lithography techniques and anisotropic etching. The first experiments into this direction are encouraging
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
Controlled inter-state switching between quantized conductance states in resistive devices for multilevel memory
A detailed understanding of quantization conductance (QC), their correlation
with resistive switching phenomena and controlled manipulation of quantized
states is crucial for realizing atomic-scale multilevel memory elements. Here,
we demonstrate highly stable and reproducible quantized conductance states
(QC-states) in Al/Niobium oxide/Pt resistive switching devices. Three levels of
control over the QC-states, required for multilevel quantized state memories,
like, switching ON to different quantized states, switching OFF from quantized
states, and controlled inter-state switching among one QC states to another has
been demonstrated by imposing limiting conditions of stop-voltage and current
compliance. The well defined multiple QC-states along with a working principle
for switching among various states show promise for implementation of
multilevel memory devices
A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning
Nanoscale resistive memories are expected to fuel dense integration of
electronic synapses for large-scale neuromorphic system. To realize such a
brain-inspired computing chip, a compact CMOS spiking neuron that performs
in-situ learning and computing while driving a large number of resistive
synapses is desired. This work presents a novel leaky integrate-and-fire neuron
design which implements the dual-mode operation of current integration and
synaptic drive, with a single opamp and enables in-situ learning with crossbar
resistive synapses. The proposed design was implemented in a 0.18 m CMOS
technology. Measurements show neuron's ability to drive a thousand resistive
synapses, and demonstrate an in-situ associative learning. The neuron circuit
occupies a small area of 0.01 mm and has an energy-efficiency of 9.3
pJspikesynapse
Process Optimization and Downscaling of a Single Electron Single Dot Memory
This paper presents the process optimization of a single-electron nanoflash
electron memory. Self-aligned single dot memory structures have been fabricated
using a wet anisotropic oxidation of a silicon nanowire. One of the main issue
was to clarify the process conditions for the dot formation. Based on the
process modeling, the influence of various parameters (oxidation temperature,
nanowire shape) has been investigated. The necessity of a sharp compromise
between these different parameters to ensure the presence of the memory dot has
been established. In order to propose an aggressive memory cell, the
downscaling of the device has been carefully studied. Scaling rules show that
the size of the original device could be reduced by a factor of 2. This point
has been previously confirmed by the realization of single-electron memory
devices
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