56 research outputs found

    AREA-TIME OPTIMAL ADDER WITH RELATIVE PLACEMENT GENERATOR

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    ABSTRACT This paper presents design of an adder generator, for the production of area-time-optimal adders. A unique feature of the proposed generator is its integrated synthesis and layout environment achieved by providing relative placement information to the synthesis tool. Adders produced by this generator are dynamically configured for a given technology library, wire-load model, delay, and area goal. The adder architecture used in this generator is a hybrid of Brent & Kung, carry select, and ripple carry adders. When compared with standard cell fast adders, a 20%-50% reduction in area with comparable delays is achieved. The reduction comes from a judicious selection of ripple carry or carry select adders based on computation of delays. When performance is being met, the carry select adders are replaced with ripple carry adders. The proposed generator has been integrated into a commercially available high-performance datapath design tool

    Digital System Clocking: High-Performance and Low-Power Aspects

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    High-performance system design: circuits and logic

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    Application of logical effort techniques for speed optimization and analysis of representative adders

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    This paper presents the transistor-level analysis of contemporary 64-bit adders. The logical effort technique was applied to provide more descriptive presentation of the delay and circuit architecture. It also enabled optimization of gate size for optimal performance. The selected adders were dynamic carry-lookahead adder (DCLA), static carry-select adder (SCSA), dynamic Kogge-Stone adder (DKSA) and Ling/conditional-sum adder (DLCNSA). The results matched well with simulation using 0.18µm, 1.8V CMOS. Adders with fewer levels in the critical path showed superior performance. In particular, for dynamic adders, a 0.6-FO4 per-gate delay improvement was observed. 1
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