Further characterisation of digital pixel test structures implemented in a 65 nm CMOS process

Aglieri Rinella G; Apadula N; Andronic A; Antonelli M; Aresti M; Baccomi R; Becht P; Beole S; Borri M; Braach J; Buckland MD; Buschmann E; Camerini P; Carnesecchi F; Cecconi L; Charbon E; Contin G; Dannheim D; de Melo J; Deng W; di Mauro A; Hasenbichler J; Hillemanns H; Hong GH; Isakov A; Jang H; Junique A; Kim M; Kluge A; Kotliarov A; Křížek F; Lautner L; Lim S; Mager M; Marras D; Martinengo P; Masciocchi S; Menzel MW; Munker M; Piro F; Rachevski A; Rebane K; Reidt F; Russo R; Sanna I; Sarritzu V; Senyukov S; Snoeys W; Sonneveld J; Šuljić M; Svihra P; Tiltmann N; Di Trapani V; Usai G; Van Beelen JB; Vassilev MD; Vernieri C; Villani A

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oai:purl.org/net/epubs:work/63348247

Further characterisation of digital pixel test structures implemented in a 65 nm CMOS process

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Last time updated on 24/11/2025

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