Energy-Saving Triggering Series Low-Power, High-Performance Locking Systems for Element Design: Pseudo NMOS

Abstract

Flip-flops represent a significant source of power dissipation within a system. The clocking system itself comprises sequential components, such as latches and flip-flops, alongside the network that delivers clock signals. The pseudo-NMOS technology, split path, and clock tree sharing schemes are employed to propose a positive edge triggering flip-flop that is designed for both speed and power efficiency. The flip-flop's latching section's floating node instability and inadequate circuit energy loss are solved via pseudo NMOS and split path approaches, respectively. By enabling the latching part of the flip-flop to share the clock provision network for gathering the data D, the clock tree sharing technique reduces the D-Q delay and the overall number of transistors required to construct the clock provision network. Cutting back on the number of clocked loads is one method that reduces dynamic power dissipation and switching activity. The flip-flop’s latching part is made using this process in the suggested design. This study evaluates the performance of a flip-flop circuit modeled using 0.12 nm CMOS process technology. According to the simulation comparison, the suggested register element design improves The power delay product increased from 56.86th% to 71.26th%, the energy delay product rose from 77.86th% to 82.4th%, and the power energy product (PEP) escalated from 56.22th% to 81.22th%. It conserves between 7.06th% and 32.83rd% of energy