Comparative Architecture of Cryptographic Algorithms using Verilog

Abstract

Applications of cryptography range over secure communications and storage. The cryptographic algorithms have found their place in the implementation of Advanced Encryption Standard, which has emerged as a widely adopted standard for its robustness and efficiency. This report begins with a comparative study regarding the architectural issues of the AES cryptographic algorithm implementation using Verilog, which is a hardware description language. This paper only focuses on the simulation of two different modes of encryption under AES, namely Cipher Block Chaining mode and Electronic Codebook mode. While simulating, the study probes into minute details of architecture for each cryptographic mode and brings out relative strengths, weaknesses, and performance characteristics. The Verilog-based simulations establish how each mode would carry out its operations at the hardware level and hence help study efficiencies and complexities. This comparative analysis is supposed to enable judgment on the trade-offs CBC and ECB modes represent in considerations like speed, resource utilization, and security. This work shall serve as a foundation for the further enhancement and optimization of AES implementations, enabling development in secure data transit and storage systems. Drawing on the conclusions of side arguments, this report lays the foundation for an investigation into the architectural intricacies of cryptographic algorithms and serves as a building block toward taking on further research in hardware-based cryptography