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Two Timing Samplers

By Edward H. Frank and Robert F. Sproull

Abstract

Testing VLSl chips presents a variety of problems. some of which can be solved by building on-chip testing\ud structures. On-chip testing structures can allow a designer to test aspects of a circuit which might be difficult to\ud test even with expensive test equipment and moreover can provide reasonable testing hardware to designers who\ud do not have access to sophisticated off-chip testing equipment.\ud \ud In this paper we describe a type of on-chip test structure called H timing sampler which enables the designer to\ud accurately measure when on-chip signal transitions occur. The timing samplers we present are simple. They\ud have been fabricated as part of a multi-project chip and experimental results show that they arc reasonably\ud accurate as well

Publisher: California Institute of Technology
Year: 1981
OAI identifier: oai:caltechconf.library.caltech.edu:222
Provided by: CaltechCONF

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Citations

  1. (1978). A logic design ~tructure for LSI testability. 0 ns (min) 2 ns (min) 0 n~ (min) 2 ns (min) 32 n'l (min) 30 ns (max) 12ns (min) ton~ (max ) &quot;Journal of De.liJ<II Automation and Fault Tolemnt Computing&quot;

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