The investigation of the diameter dimension effect on the Si nano-tube transistors

Abstract

The vertical gate-all-around (V-GAA) Si nano-tube (NT) devices with different diameter dimensions are studied in this work with the promising device performance. The V-GAA structure makes the transistor easy to be scaled down continuously to meet the complementary metal-oxide-semiconductor (CMOS) scaling requirements of the 7/10 nm technology node and beyond. The Si NT device with the hollow structure is demonstrated to have the capability to “deplete” and “screen-out” the out-of gate control carriers in the center of the NT and further result in the better device short channel control. Based on the study in this work, the V-GAA Si NT device with the optimized diameter dimension (=20 nm) can benefit the Ion-state current and reduce the Ioff-state stand-by power simultaneously, due to the less surface roughness scattering and the better short channel control characteristics. The proposed V-GAA Si NT device is regarded as one of the most promising candidates for the future application of the sub-7/10 nm logic era