From STM to nanomemory: a transfer of technology feasibility study

Abstract

Recent years have seen exponential increase in memory capacity for computer data storage. Increased bit density has been produced by decreasing feature sizes in microelectronic fabrication. As minimum microelectronic feature sizes are realized, new methods are being investigated to continue the increase in recording bit density. This report examines features which are necessary to produce an electron-tunneling based memory which is postulated to increase the data density by a factor of 105-106 over current manufactured memories. A description is given for combining tunneling microscopy with memory technology to achieve this high density memory. Experiments using a tunneling tip to produce nanometer scale features on a surface are recounted. The repeatability and durability of the produced features are investigated with a summary of these aspects included for various materials reported in the literature. Some necessary mechanical and electrical design criteria for a tunneling memory are obtained. Observed and reported inconsistency in nanometer lithography are attributed to nonpredictable tunneling currents and resulting tip-sample separations. Experimental and theoretical work scrutinizing tunneling currents as a function of tip-sample displacement is included. Other factors affecting the practicality of a tunneling based memory are also incorporated