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A low-power asynchronous VLSI FIR filter

By Viv A. Bartlett and Eckhard Grass

Abstract

An asynchronous FIR filter, based on a Single Bit-Plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its\ud coeflcient-set. The proposed architecture has the property that coefficients in a Sign-Magnitude representation can be handled at negligible overhead which, for typical filter\ud coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput.\ud Transistor level simulations show energy consumption to be lower than in previously reported designs.\u

Topics: UOW3
Publisher: IEEE Computer Society
OAI identifier: oai:westminsterresearch.wmin.ac.uk:901
Provided by: WestminsterResearch

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Citations

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