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Designing multiplier blocks with low logic depth\ud

By Andrew G. Dempster, Suleyman S. Demirsoy and Izzet Kale


The depth of logic in an integrated circuit, particularly a CMOS circuit, is highly correlated both with power consumption and degraded switching speed. Hence, designs with low logic depth can aid in reducing power consumption and increasing switching speed. In this paper we demonstrate how new and modified algorithms have been used to design multiplier blocks with low logic depth and power consumption

Topics: UOW3
Publisher: IEEE Computer Society
OAI identifier: oai:westminsterresearch.wmin.ac.uk:960
Provided by: WestminsterResearch

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