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Power consumption behaviour of multiplier block algorithms

By Suleyman S. Demirsoy, Andrew G. Dempster and Izzet Kale


Multiplier blocks have been used primarily for the reduction of circuit complexity. Using new algorithms, it has been shown that they can also be used for effective reduction of power consumption in digital filter circuits. In this paper, the new GP score method is used as a relative power measure to compare digital filter multiplier blocks using the BHM, RAGn and CI algorithms

Topics: UOW3
Publisher: IEEE Computer Society
OAI identifier:
Provided by: WestminsterResearch

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