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Synthesis of reconfigurable multiplier blocks: part II: algorithm

By Suleyman S. Demirsoy, Izzet Kale and Andrew G. Dempster

Abstract

Reconfigurable Multiplier Blocks (ReMB) offer significant area, delay and possibly power reduction in time-multiplexed\ud implementation of multiple constant multiplications. This paper and its companion paper (entitled Part I- Fundamentals) together present a systematic synthesis\ud method for Single Input Single Output (SISO) and Single\ud Input Multiple Output (SIMO) ReMB designs. This paper\ud illustrates the synthesis method through examples. The\ud companion paper presents the necessary foundation and\ud terminology needed for developing a systematic synthesis\ud technique. The proposed method achieves reduced logic-depth\ud and area over standard multipliers / multiplier blocks

Topics: UOW3
Publisher: IEEE Computer Society
OAI identifier: oai:westminsterresearch.wmin.ac.uk:967
Provided by: WestminsterResearch

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Citations

  1. (2003). Complexity Reduction in Digital Filters and Filter Banks”,
  2. (2004). Efficient Implementation of Digital Filters using Reconfigurable Multiplier Blocks”, .Asilomar Conf. on Signal, Systems and Computers,November
  3. Synthesis of reconfigurable multiplier blocks:Part I-Fundamentals”,
  4. (1995). Use of minimum-adder multiplier-blocks in FIR digital filters”,

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