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A high-speed, low-power interleaved trace-back memory for Viterbi decoder\ud

By Pasin Israsena and Izzet Kale

Abstract

This paper presents a high-speed, low-power trace-back memory structure for a Viterbi decoder. The new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly. The trace-back memory is internally interleaved such that high-speed characteristic is achieved while low-power consumption is maintained. The structure is used together with appropriate clock and power-aware control signals. The design is 100% portable and is suitable for a SoftIP approach. Based on the AMS 0.35 /spl mu/m CMOS implementation the trace-back memory is estimated to consume energy of 232 pJ, which is 53.6% less than a conventional RAM based design, with a maximum throughput of 1.1 Gbps

Topics: UOW3
Publisher: IEEE
OAI identifier: oai:westminsterresearch.wmin.ac.uk:3337
Provided by: WestminsterResearch

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