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A new structure for capacitor-mismatch-insensitive multiply-by-two amplification

By Hashem Zare-Hoseini, Omid Shoaei and Izzet Kale

Abstract

A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity to capacitors' mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (/spl times/2). Comparing to the conventional multiply-by-two gain-stage, the mismatches between the capacitors has a much smaller influence on the accuracy of the gain of two (/spl times/2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35/spl mu/m CMOS technology

Topics: UOW3
Publisher: IEEE
OAI identifier: oai:westminsterresearch.wmin.ac.uk:3339
Provided by: WestminsterResearch

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