Skip to main content
Article thumbnail
Location of Repository

Implementation of MAC by using Modified Vedic Multiplier

By Sreelekshmi M. S., Farsana F. J., Jithin Krishnan, Rajaram S and Aneesh R

Abstract

Multiplier Accumulator Unit (MAC) is a part of Digital Signal Processors. The speed of MAC depends on the speed of multiplier. So by using an efficient Vedic multiplier which excels in terms of speed, power and area, the performance of MAC can be increased. For this fast method of multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among various method of multiplication in Vedic mathematics, Urdhva Tiryagbhyam is used and the multiplication is for 32 X 32 bits. Urdhva Tiryagbhyam is a general multiplication formula applicable to all cases of multiplication. Adder used is Carry Look Ahead adder. The proposed design shows improvement over carry save adder

Topics: MAC, Vedic multiplier, VHDL, Science, Q, Mathematics, QA1-939, Instruments and machines, QA71-90, Electronic computers. Computer science, QA75.5-76.95
Publisher: Association of Computer Communication Education for National Triumph (ACCENT)
Year: 2013
OAI identifier: oai:doaj.org/article:dfd8d4ff158d4fec9e64c990f6922352
Journal:
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • https://doaj.org/toc/2277-7970 (external link)
  • https://doaj.org/toc/2249-7277 (external link)
  • http://accentsjournals.org/Pap... (external link)
  • https://doaj.org/article/dfd8d... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.