Deadlock Analysis for a Fault-Tolerant System

Abstract

. This article presents an approach for the verification of communication properties in large-scale real-world embedded systems by means of formal methods. It is illustrated by examples and results obtained during an industrial verification project performed for a faulttolerant system designed and implemented by Daimler-Benz Aerospace for the International Space Station ISS. The approach is based on CSP specifications and the model-checking tool FDR. The task is split into manageable subtasks by applying an abstraction technique for restricting the specifications to the essential communication behaviour, modularization according to the process structure, and a set of generic theories developed for the application. 1 Introduction One of the essential obstacles for the acceptance of formal methods during the last years is their failure to scale up to realistic applications. In our experience this problem can only be overcome by a combination of methods and the use of suitable tools that..