Abstract- Phased lock loop is a control system that generates an output signal whose phase of an input reference signal. This compares the phase of the input signal with the phase derived from its output oscillator adjusts the frequency of its oscillator to keep the phase matches. The signal from the phase detector is used to control the oscillator in a feedback loop. As such a operational device the PLL has wide range of application s in telecommunication, computers and electronic applications. The phase locked loop consists of frequency oscillator and a phase detector. The work represents the layout design of Phased Lock loop PLL with multiple outputs. Effort has been made to design ultra low power design and it is implemented using ultra low power sub threshold D flip flop. The proposed architecture is implemented for 45nm CMOS technology. This is carried out for the inner electronics of all sub blocks like oscillator and phase detector. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The design implemented in analog design tool like Microwind 3.1 where each sub block is designed at its ultra low power design
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