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Performance Evaluation of Low Power MIPS Crypto Processor based on Cryptography Algorithms Kirat Pal Singh 1, Dilip Kumar 2

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Abstract

This paper presents the design and implementation of low power 32-bit encrypted and decrypted MIPS processor for Data Encryption Standard (DES), Triple DES, Advanced Encryption Standard (AES) based on MIPS pipeline architecture. The organization of pipeline stages has been done in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of three standard cryptography algorithms on MIPS processor and dependency among themselves are explained in detail with the help of a block diagram. Clock gating technique is used to reduce the power consumption in MIPS crypto processor. This approach results in processor that meets power consumption and performance specification for security applications. Proposed Implementation approach concludes higher system performance while reducing operating power consumption. Testing results shows that the MIPS crypto processor operates successfully at a working frequency of 218MHz and a bandwidth of 664Mbits/s

Topics: Datapath, Throughput, MIPS
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.416.6779
Provided by: CiteSeerX
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