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Cadence Design of Leakage Power Reduction Circuit in CMOS VLSI Design

By K. R. N. Karthik, M. Nagesh Babu, V. Narasimhanayak and S. Rajeswari

Abstract

In this paper, a low-power novel design technique proposed in [1] to minimize the standby leakage power, in nanoscale CMOS very large scale integration (VLSI) systems by generating the reverse body-bias voltage, is applied to op-amp circuit and the stack circuit. The optimal reverse body-bias voltage is generated from the proposed leakage circuit, and calculated the subthreshold current (ISUB) and the band-to-band tunneling current (IBTBT). The proposed circuit will be simulated in Cadence 180 nanometer CMOS technology

Topics: sub-threshold Leakage, Band to Band Tunneling currents
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.415.1385
Provided by: CiteSeerX
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