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Republic of China and

By Tung-yang Ho, Lih-hsing Hsu, Chang-hsiung Tsai and Jeng-yan Hwang

Abstract

Given a series-parallel network Ž network, for short. N, its dual network N is given by interchanging the series connection and the parallel connection of network N. We usually use a series-parallel graph to represent a network. Let GN � � and GN � � be graph representations of N and N, respectively. A sequence of edges e, e,...,e is said to form a common trail on ŽGN,GN � � � �. 1 2 k if it is a trail on both GN � � and GN � �. If a common trail covers all of the edges in GN � � and GN � �, it is called a double Euler trail. However, there are many different graph representations for a network. We say that a network N has a double Euler trail Ž DET. if there is a common Euler trail for some GN � � and some GN � �. Finding a DET in a network is essential for optimizing the layout area of a complementary CMOS functional cell. Maziasz and Hayes Ž IEEE Trans. Computer-Aided Design 9 Ž 1990., 708�719. gave a linear time algorithm for solving the layout problem in fixed GN � � and GN � � and an exponential algorithm for finding the optimal cover in a network without fixing graph representations. In this paper, we study properties of subnetworks of a DET network. According to these properties, we propose an algorithm that automatically generates the rules for composition of trail cover classes. On the basis of these rules, a linear time algorithm for recognizing DET networks is presented. Furthermore, we also give a necessary and sufficient condition for the existence of a double Euler circuit in a network

Year: 1994
OAI identifier: oai:CiteSeerX.psu:10.1.1.414.8818
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