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Verification and Simulation of New Designed NAND Flash Memory Controller

By Koushel Agarwal, Vijay Kumar Magraiya, Dr. Anil and Kishore Saxena

Abstract

Abstract — In this paper a NAND flash memory controller was designed. For the better use of NAND type flash memory we design a new Arithmetical and Logical Unit (ALU) for calculating addition, subtraction, increment, decrement operations etc. In this memory controller we design a decoder, single memory cell, memory module etc. These all are encapsulated inside a controller and this is on top most in hierarchy. As the cell size of NAND flash memory is reduced every year the performance, reliability, speed is increased very rapidly. NAND flash memory is programmed on page by page basis. Typically programming time is very less few micro second per page. This NAND flash memory controller architecture can be used with a real secure digital card, multimedia card (SD/MMC), digital cameras etc. Experimental results show that the designed controller give good performance and full fill all the system specifications. We design and implement FPGA based open framework for fast, correct features of flash memories

Topics: Arithmetical and Logical Unit (ALU, Encapsulation, Field Programmable Gate Array (FPGA
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.414.1818
Provided by: CiteSeerX
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