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Cost/Performance Analysis of a Multithreaded PIM Architecture

By Shyamkumar Thoziyoor, Shannon K. Kuntz, Jay B. Brockman and Peter M. Kogge

Abstract

Many research projects over the past decade have explored embedding processing logic into the memory system of a computer as a means to enhance performance. An obstacle to widespread acceptance of processing-in-memory (PIM) has been the increased cost-per-bit of embedded memory as compared to high-volume commodity memory. Using analytic models, this paper examines the performance and volume production silicon costs for a PIM-enhanced system with multithreading in the memory, versus a baseline system with commodity DRAM. The paper provides insight into the question of which PIM configurations would provide cost-effective performance if they were produced in high volume

Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.413.4953
Provided by: CiteSeerX
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