Location of Repository

Performance Analysis of NoC Architectures

By Anitha G, Muralidharan D and Muthaiah R

Abstract

Abstract: Network-on-chip (NoC) architecture grants the communication frame work for SoC design.The Performance dominating factors of NoC are architecture, node’s size, and the routing algorithm. Various routing algorithms are proposed for the router design in Network on chip(NoC).According to the requirements of NoC application, analysis and simulations for various routing algorithms, such as C-routing, ADBR and adaptive congestion aware routing algorithm are considered for this work. The simulation results shows that Congestion aware adaptive routing algorithm has better performance than others. Here, the new adaptive routing algorithm by merging the features of ADBR and adaptive congestion aware routing algorithm has been discussed

Topics: NoC, Routing algorithms and Performance analysis. I.INTRODUCTION The
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.412.7
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.enggjournals.com/ij... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.