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Two Adaptive Hybrid Cache Coherency Protocols

By Craig Anderson and Anna R. Karlin

Abstract

We present and evaluate adaptive, hybrid cache coherence protocols for bus-based, shared-memory multiprocessors. Such protocols are motivated by the observation that sharing patterns vary substantially between different programs and even cache blocks within the same program. Performance measurements across a range of parallel applications indicate that the adaptive protocols we present perform well compared to both Write-Invalidate and Write-Update protocols. 1 Introduction In a bus-based multiprocessor, bus contention can lead to increased program execution time because a processor may stall while its cache is waiting for the bus. For many interesting applications, the bus transactions required to maintain cache coherence are the main source of contention. It is known that no single, non-adaptive cache coherence protocol minimizes bus contention for all applications or even for all cache blocks within the same application. In this paper, we present and evaluate new coherence protoco..

Year: 1996
OAI identifier: oai:CiteSeerX.psu:10.1.1.36.536
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