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Lattice Diagrams Using Reed-Muller Logic

By Marek A. Perkowski, Malgorzata Chrzanowska-Jeske and Yang Xu


Universal Akers Arrays (UAA) allow to realize arbitrary Boolean function directly in cellular layout but are very area-inefficient. This paper presents an extension of UAAs, called "Lattice Diagrams" in which Shannon, Positive and Negative Davio expansions are used in nodes. An efficient method of mappig arbitrary multi-output incompletely specified functions to them is presented. We prove that with these extensions, our concept of regular layout becomes not only feasible but also efficient. Regular layout is a fundamental concept in VLSI design which can have applications to submicron design and designing new fine-grain FPGAs. 1 INTRODUCTION. Akers defined Universal Akers Arrays (UAA) to realize arbitrary Boolean functions in a regular and planar layout [1]. UAA is a rectangular array of identical cells, each of them being a multiplexer, where every cell obtains signals from South and East and gives its output to North and West. All cells on a diagonal are connected to the same (con..

Year: 1997
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