Skip to main content
Article thumbnail
Location of Repository

International Journal of Electrical and Computer Engineering 3:12 2008 A high Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates

By Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy and Hiranmay Saha

Abstract

Abstract—The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15�m and 0.35�m technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE. Keywords—XOR gate, full adder, improvement in speed, area minimization, transistor count minimization. I

Year: 2013
OAI identifier: oai:CiteSeerX.psu:10.1.1.359.8711
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.waset.org/journals/... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.