Abstract—This paper describes a system-level approach to improve the latency of FPGA designs byperforming optimization of the design specification on a functional level prior to highlevel synthesis. The approach uses Taylor Expansion Diagrams (TEDs), a functional graph-based design representation, as a vehicle to optimize the dataflow graph (DFG) used as inputto the subsequent synthesis. The optimization focuses on critical path compaction in the functional representation before translating it into a structural DFG representation. Our approach engages several passes of a traditional high-level synthesis (HLS) process in a simulated annealing-based loop to make efficient cost tradeoffs.Thealgorithmistimeefficientandcanbeusedforfastdesign space exploration. The results indicate a latency performance improvement of 22 % on average versus HLS with the initial DFG for a series of designs mapped to Altera Stratix II devices. I
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