Several topological optimization techniques have been developed to minimize the area of PLAs. Significant yield enhancement can also be achieved by minimizing the defect sensitivity of a design that is already optimized for area. In this paper, we propose a yield enhancement technique through which the defect sensitivity of the design will be minimized without increasing the area. This reduction in critical area is achieved primarily by minimizing the wire lengths in several layers of the layout. The yield enhancement results of the proposed technique on some benchmark PLA examples are presented.
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