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A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving50.9dBSNDRand3dBEffective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS

By Dušan Stepanović, Borivoje Nikolić and Senior Member

Abstract

Abstract—This paper presents a power- and area-efficien

Topics: Index Terms—A/D, ADC, background, calibration, CMOS, converters, linearity, SAR, time-interleaved, timing
Year: 2013
OAI identifier: oai:CiteSeerX.psu:10.1.1.352.7494
Provided by: CiteSeerX
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