STRUCTURING REVERSIBLE CIRCUIT TO OVERCOME LOW-POWER DISSIPATION

Abstract

This paper presents a design methodology for that realization of Booth’s multiplier in reversible mode. Booth’s multiplier is recognized as among the fastest multipliers in literature so we have proven a competent design methodology in reversible paradigm. Reversible logic attains the attraction of researchers within the last decade mainly because of low-power dissipation. Designers’ endeavors therefore are ongoing in creating complete reversible circuits composed of reversible gates. All of the theorems provide lower bounds for quantity of gates, garbage outputs, circuit delay and quantum cost. The important thing achievement from the design is, it is capable of doing dealing with both signed and unsigned figures, which isn't contained in the present circuits considered within this paper. We assess the 4×4 form of the suggested Booth’s multiplier using the two existing designs. Theoretical underpinnings, established for that suggested design, reveal that the suggested circuit is extremely efficient from reversible circuit design perspective. The suggested architecture is capable of doing performing both signed and unsigned multiplication of two operands without getting any feedbacks, whereas existing multipliers in reversible mode consider loop that is strictly disallowed reversible logic design