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A Study of Theoretical Issues in the Synthesis of Delay Fault Testable Circuits

By Sreejit Chakravarty

Abstract

Several useful multilevel logic optimization transformations (MLOT), not known to preserve path delay fault testability (PDFT), are shown to indeed do so. We show that, while minimizing area, a number of MLOTs can also be used to "improve" PDFT! A sufficient condition for identifying PDFT unate circuits is presented. We show how these results can be used to: improve a known method for synthesizing PDFT circuits; and to prove the PDFT of designs not known to be so. INDEX TERMS: Delay Fault Testable Circuits; Logic Optimization; Logic Synthesis; Testability Enhancing Tranformations; Testability Preserving Transformations. 1 Introduction Delay testing attempts to verify the timing specifications of circuits. Two models for delay testing are: path delay testing[6, 10, 11, 14, 18]; and gate delay testing[6]. We assume path delay testing that uses the path delay fault model discussed below. Along every physical path, from an input to an output of the combinational circuit, two distinct tr..

Topics: INDEX TERMS, Delay Fault Testable Circuits, Logic Optimization, Logic Synthesis, Testability Enhancing Tranformations, Testability Preserving Transformations
Year: 1993
OAI identifier: oai:CiteSeerX.psu:10.1.1.32.5776
Provided by: CiteSeerX
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