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PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor

By F. Scherber, E. Barke and W. Meier

Abstract

Layout verification of VLSI circuits can be speeded up significantly by parallel execution. The approach described in this paper combines parallel and hierarchical verification of cells and cell areas using geometrical partitioning. In contrast to earlier approaches, design rule check and netlist extraction are performed in parallel without any functional restriction. This is accomplished by a new concept called multiple execution switching. Thus, industrial leading edge VLSI circuits can be handled. High speedups are obtained for large real-world layouts. A productive use is possible and will reduce time-to-market considerably. 1 Introduction Complete layout verification of today's leading edge VLSI circuits is only possible by exploiting the inherent hierarchy and regularity of a chip design [1]. Using hierarchical design rule checking and netlist extraction decreases computation time and data volume substantially. In addition, the number of reported errors is reduced significantly..

Year: 1996
OAI identifier: oai:CiteSeerX.psu:10.1.1.32.2768
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