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High-Level Synthesis of Gracefully Degradable ASICs

By Wah Chan and Alex Orailoglu

Abstract

We propose a novel graceful degradation scheme, L/U reconfiguration, which can tolerate a single permanent fault in each hardware class of ASIC datapaths. In the proposed scheme, dynamic hardware rebinding and operation rescheduling are performed by a systematic perturbation of the original configuration. A high-level synthesis procedure, which automatically generates such fault-tolerant systems, is also presented. Experiments show that our reconfigurable AISC designs, as compared to optimal nonfault -tolerant designs, achieve optimal pre-reconfiguration and near-optimal post-reconfiguration speed performance. 1 Introduction Graceful degradation, a time redundancy approach [2], tolerates permanent faults by using dynamic reconfiguration. Unlike standby sparing, graceful degradation enables high levels of hardware utilization both before and after reconfiguration and demands smaller levels of interconnection. It is most suitable for applications where small chip area and superior init..

Year: 1996
OAI identifier: oai:CiteSeerX.psu:10.1.1.32.1106
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