In this paper we describe a Time Warp based parallel implementation of an event driven logic simulator on a distributed memory multiprocessor (iPSC/860). The Basic Time Warp mechanism has been compemented with an optimized method for incremental state saving and a mechanism that optimizes re-simulation of a rolled back period of simulated time for those elements that are very complex to evaluate. In addition to static partitioning where elements are distributed to partitions either randomly or by using a min-cut algorithm dynamic repartitioning is possible in out implementation. For our measurements, we used a set well-known benchmark circuits. Speedups showed to be strongly dependent on the circuit being simulated, its input stimuli and on the way circuits are partitioned. However, one observation has been made with all the workloads: The simulators' lvt's tend to diverge extremly throughout the simulation. Even though memory requirements for state saving have been minimized, simulat..