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Verification Of Abstracted Instruction Cache of TITAC2: A Case Study

By A Case Study and Tomohiro Yoneda

Abstract

In this paper, we demonstrate the formal verification of a practical timed asynchronous circuit. The target circuit is obtained by abstracting the instruction cache subsystem of a real asynchronous processor, TITAC 2. We also show several techniques to improve our verification method. The improved verifier could verify the target circuit in approximately 15 minutes, using less than 20 MBytes of memory. Keywords: Formal verification, timed asynchronous circuits, partial order reduction, time Petri nets, instruction cache. 1. INTRODUCTION In order to avoid the various di#culties which arise in designing large synchronous circuits, such as clock skews, high power consumption, and so on, designing asynchronous circuits without any clock systems has been attracting notice. In fact, several research groups demonstrated that an entire microprocessor could be designed and fabricated in this manner[Martin et al., 1989; Furber et al., 1994; Furber et al., 1996; Nanya et al., 1994; Takamura et..

Topics: Formal verification, timed asynchronous circuits, partial order reduction, time Petri nets, instruction cache
Year: 1999
OAI identifier: oai:CiteSeerX.psu:10.1.1.31.328
Provided by: CiteSeerX
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