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Clean formal semantics for VHDL

By Peter T. Breuer, Luis Sánchez Fernández, Carlos Delgado Kloos and Ez Carlos Delgado Kloos


A simple formal semantics for the standard hardware description language vhdl is set out in functional style. The presentation comprises an executable specification for a synchronously clocked vhdl simulator. 1 Introduction This paper attempts to lay the basis for simpler formal semantics for vhdl than available in the literature. Vhdl is a standardized hardware description language developed in the 1980s with the support of the US DoD, and it has gained wide acceptance. No formal semantics underpins the standard [4], and there has been great interest in developing a formal semantics for the simulation model it defines. Timing aspects are formalized in [7], but [9] appears to be the most complete and satisfactory formalization to date. It sets out an asynchronous operational semantics for vhdl simulators. In contrast, we set out a synchronous semantics. Vhdl is seen as a side-effect on a clocked sequence of global states; one for every unit interval of time. A good formal semantics..

Year: 1994
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