Location of Repository

Layout-constrained Retargeting of Analog Blocks

By R. Castro-lópez, F. V. Fernández, M. Delgado-restituto, F. Medeiro and A. Rodríguez-vázquez

Abstract

This paper introduces a complete methodology for retargeting of transistor-level circuits to different sets of specifications. By careful integration of the device sizing and layout generation tasks, fully functional designs are generated in a few minutes of CPU time. The methodology is illustrated via the retargeting of a fully-differential Miller-compensated two-stage operational amplifier for a new set of specifications. 1

Year: 2011
OAI identifier: oai:CiteSeerX.psu:10.1.1.191.125
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.imse.cnm.es/esd-msd... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.