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A Regular VLSI Array for an Irregular Algorithm

By Florent De Dinechin, Doran K. Wilde, Sanjay Rajopadhye and Rumen Andonov

Abstract

Abstract. We present an application specific, asynchronous VLSI processor array for the dynamic programming algorithm for the 0/1 knapsack problem. The array is derived systematically, using correctnesspreserving transformations, in two steps: the standard (dense) algorithm is first transformed into an irregular (sparse) functional program which has better efficiency. This program is then implemented as a modular VLSI architecture with nearest neighbor connections. Proving bounds on buffer sizes yields a linear array of identical asynchronous processors, each with simple computational logic and a pair of fixed size FIFOs. A modular solution can be obtained by additional load-time control, enabling the processors to pool their buffers.

Year: 2011
OAI identifier: oai:CiteSeerX.psu:10.1.1.189.865
Provided by: CiteSeerX
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