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Investigation of Performance Metrics for Interconnect Stack Architectures

By Puneet Gupta, Andrew B. Kahng, Youngmin Kim and Dennis Sylvester

Abstract

This paper discusses metrics involving the bandwidth and energy characteristics of arbitrary interconnect stacks. Front-end dimensions are set by lithography and related fabrication restrictions and its performance is easily quantified using wellknown metrics such as FO4 or ring oscillator delays, Ioff, and Ion. Back-end dimensions are not similarly constrained yet there are no comparable back-end metrics. In this study we seek figures-ofmerit for interconnect architectures (stacks) that describe performance in terms of bandwidth and energy while considering issues such as via blockage and repeaters. A definition of bandwidth is presented and then appropriate via blockage models for interconnect stacks are investigated. In this paper, we improve existing bandwidth and throughput-driven design methodologies by looking at the entire stack rather than a single wiring layer. We also propose the use of bandwidth per unit energy. We evaluate and discuss these metrics in current 130nm and 90nm interconnect technologies

Topics: Measurement, performance, design. Keywords Bandwidth, Throughput, Energy, Back-end metrics, Interconnect stacks, via
Year: 2011
OAI identifier: oai:CiteSeerX.psu:10.1.1.189.5414
Provided by: CiteSeerX
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