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By Virtex- Fpgas and Olivier Despaux

Abstract

With an increasing need for lower latency and higher operating frequencies, memory interface IP is becoming more complex and needs to be tailored based on a number of factors such as latency, burst length, interface width, and operating frequency. The Xilinx ® Memory Interface Generator (MIG) tool enables the creation of a large variety of memory interfaces for devices such as the Virtex®-6 FPGA. However, in the Virtex-6 FPGA, QDR II SRAM is not one of the options available by default. Instead, the focus has been on the QDR II+ technology using four-word burst access mode. This application note presents a Verilog reference design that has been simulated, synthesized, and verified on hardware using Virtex-6 FPGAs and QDR II SRAM two-word burst devices

Year: 2010
OAI identifier: oai:CiteSeerX.psu:10.1.1.185.2581
Provided by: CiteSeerX
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