Location of Repository

A Low-Resource AES Encryption Circuit Using Dynamic Reconfiguration

By Peera Thontirawong and Prabhas Chongstitvatana

Abstract

This paper presents an implementation of an Advanced Encryption Standard (AES) encryption unit using dynamic reconfiguration based on the Xilinx Spartan-3 FPGA platform. The proposed design reuses resource of FPGA by adapting dynamic reconfiguration to reduce the number of resource used in the circuit. By changing circuits at runtime, the size of the whole circuit is limited to the largest reconfigurable module. The implementation of the dynamic reconfigurable AES encryption unit on XC3S200-4FT256 requires only 359 slices, while achieving throughput about 18 Kbps, and 16 Mbps if assume that there is no reconfiguration delay

Topics: Key Words, AES, FPGA, Dynamic Reconfiguration
Year: 2011
OAI identifier: oai:CiteSeerX.psu:10.1.1.184.3219
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.cp.eng.chula.ac.th/... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.